Engineering Homework Help

Do the extra credit for a tip

Write a report that contains the following:
i. Your Verilog design code. Use:
i. Device: Zyboboard (XC7Z010- -1CLG400C)
ii. Your Verilog® TestBench design code. Add “`timescale 1ns/1ps” as the first line of your testbench file.
iii. The waveforms resulting as requested from item 9 above.
iv. The design schematics from the Xilinx synthesis of your design. Do not use any area constraints.
v. Snapshot of the I/O Planning and
vi. Snapshot of the floor planning
vii. The design should be free from errors when synthesized, implemented and generated of the bitstream.